When filters are implemented in integrated circuits, the filter coefficients are stored in memory such as a read-only memory (ROM). The depth of the ROM is equal to the number of coefficients and the width of the ROM is equal to the bit-width of the coefficients. Lower quantization noise means larger bit-widths, which in turn mean a larger ROM area is required.
In high precision digital signal processing (DSP) systems using finite impulse response (FIR) filters, the coefficients of the FIR filters may need to be stored to a higher precision, and a large number of coefficients may be required to be stored. This leads to longer bit-widths and higher storage requirements. The storage requirement increases further with an increasing number of taps in each filter.
For example, if the signal-to-noise ratio (SNR) at the output of an FIR filter is high, each of the filter coefficients needs to be stored at higher precision. Such higher precision storage requires larger bit-widths for storing the coefficients. For high precision sigma-delta converters, the bit-widths can be significantly large (often more than 20 bits). Storing large numbers of high precision coefficients can take up a significant area on a silicon chip.
For the reasons stated above and for other reasons that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need for reducing the area in a silicon chip required to store digital filter coefficients.